Central Bank Digital Currencies

Today’s societal digitization continues to advance at exponential speeds driven by technology trends. Billions of Internet of Things devices have made their way into our daily lives, but also into healthcare, manufacturing, and supply chains. In contrast, the financial sector still largely operates on legacy infrastructures, where merchants receive their payments long after they released the digital/physical good to the consumer. In addition, the emergence of Decentralized Finance through blockchain technology, and the accumulation of data in private silos, have demonstrated a capacity to impact national sovereignty and monetary transmission channels. Against this backdrop, many central banks have recently started to research and test the issuance of digitally native fiat money – or Central Bank Digital Currencies (CBDCs) – in an effort to redesign the essence and use of physical cash. CBDCs present a broad variety of designs, which translate into manifold techno-legal and standardization policy questions. In this context, this chapter surveys the state-of-the art with specific focus on “retail” CBDCs. In doing so, it provides an overview of candidate architectures, heeds legal impacts and regulatory compliance issues, presents a set of case-studies and touches upon cross-border CBDC challenges

Cost-effective blockchain-based IoT data marketplaces with a credit invariant

Billions of Internet of Things (IoT) devices deployed today collect massive amounts of potentially valuable data. To efficiently utilize this data, markets must be developed where data can be traded in real time. Blockchain technology offers a potential platform for these types of markets. However, previous proposals using blockchain technology either require trusted third parties such as data brokers, or necessitate a large number of on-chain transactions to operate, incurring excessive overhead costs. This paper proposes a trustless data trading system that minimizes both the risk of fraud and the number of transactions performed on chain. In this system, data producers and consumers come to binding agreements while trading data off chain and they only settle on chain when a deposit or withdrawal of funds is required. A credit mechanism is also developed to further reduce the incurred fees. Additionally, the proposed marketplace is benchmarked on a private Ethereum network running on a lab-scale testbed and the proposed credit system is simulated so to analyze its risks and benefits

Automated silicon debug data analysis techniques for a hardware data acquisition environment

Abstract—Silicon debug poses a unique challenge to the en-gineer because of the limited access to internal signals of the chip. Embedded hardware such as trace buffers helps overcome this challenge by acquiring data in real time. However, trace buffers only provide access to a limited subset of pre-selected signals. In order to effectively debug, it is essential to configure the trace-buffer to trace the relevant signals selected from the pre-defined set. This can be a labor-intensive and time-consuming process. This paper introduces a set of techniques to automate the configuring process for trace buffer-based hardware. First, the proposed approach utilizes UNSAT cores to identify signals that can provide valuable information for localizing the error. Next, it finds alternatives for signals not part of the traceable set so that it can imply the corresponding values. Integrating the proposed techniques with a debugging methodology, experiments show that the methodology can reduce 30 % of potential suspects with as low as 8 % of registers traced, demonstrating the effectiveness of the proposed procedures. Index Terms—Silicon debug, post-silicon diagnosis, data acqui-sition setup I

Functional fault equivalence and diagnostic test generation in combinational logic circuits using conventional atpg

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.

Logic Rewiring for Delay and Power Minimization *

An application of the ATPG-based method by Veneris et al. [11] to multi-level combinational logic circuit delay and power optimization is presented. A number of theoretical results and various heuristics are described to allow for an efficient implementation of the algorithm. Experiments confirm the robustness of the approach